This paper presents a new method to reduce consumption power in flash ADC in 65NM CMOS technology. This method indicates a considerable reduction in consumption power, by removing comparators memories. The simulations used a frequency of 1 GHZ, resulting in decreased consumption power by approximately 90% for different processing corners. In addition, in this paper the proposed method was designed using interpolation technique for purpose of promoting the performance as well as decreasing the class of chip. The simulation results indicate that the consumption power for interpolation technique was decreased by approximately 5% compared to the proposed method. Also, we compare the results of the proposed technique with those of convertors frequently referred in other studies. The results show that the consumption power is considerably decreased, using the proposed technique.

This paper presents a wide spectral range Single-Photon Avalanche Diode (SPAD) implemented in 65NM standard CMOS (Complementary Metal Oxide Semiconductor) Technology. The wide wavelength sensitivity is achieved using the p-type substrate layer instead of using a different well implanted inside the substrate. The higher electron impact ionization coefficient in compare with the hole impact ionization coefficient results in an increase in the photon detection probability (PDP) in the larger wavelengths. Low PDP in compare with the older technologies is predictable according to the higher doping profiles of the modern deep-submicron technologies. Both the optical emission from the active region and spectral response detection is measured and analyzed in this paper.

Implantable image sensors have several biomedical applications due to their miniature size, light weight, and low power consumption achieved through sub-micron standard CMOS (Complementary Metal Oxide Semiconductor) technologies. The main applications are in specific cell labeling, neural activity detection, and biomedical imaging. In this paper the recent research studies on implantable CMOS image sensors for neural activity monitoring of brain are being quantified and reviewed. Based on the results, the suitable implantable image sensors for brain neural monitoring should have high signal to noise ratio of above 60 dB, high dynamic range of near 88 dB and low power consumption than the safety threshold of 4W/cm2. Moreover, it is found out that the next generation of implantable imaging device trend should reduce the pixel size and power consumption of CMOS image sensors to increase spatial resolution of sample images.

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the destine stage, an Eulerian path should be found for the logic function. Every discontinuity causes an increase in the area as well as a reduction in the clock rate and performance. The realization of a logic function using the static CMOS technology is done through different methods, most of which are based on the Uehara's method. In this paper, an algorithm is suggested that finds the Eulerian path and allows the implementation of the circuit with continuity in the diffusion region that results in minimum area. In a case where there is no Eulerian path, the possible sub-paths are found. In addition, the algorithm gives information that helps the layout generation.

The main portion of the power consumption in high speed register files is related to read out paths which are implemented using the dynamic circuits. For this reason, a new dynamic circuit technique is proposed in this paper to reduce the power consumption of the register files without significant speed and noise immunity degradation. In the proposed dynamic circuit, the pull down network is partitioned to the some smaller pull down networks to increase the circuit performance. Moreover, pull-down networks are precharged using NMOS transistors to reduce the voltage swing and hence decrease the power consumption. A 64-word x 32-bit 2-read, 1-write ported register file is implemented using the proposed circuit technique. Simulation of register files are performed using HSPICE simulator in low-Vth 90-nm CMOS technology model. Simulation results demonstrate 37% and 36% reduction in power and delay respectively at the same noise immunity compared to the conventional register file.